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NCP1083
http://onsemi.com
12
1st Class Event
Class range
Mark Range
Reset Range
2 Fingers Classification
0 V
5.4 V
9.7 V
13 V
20.5 V
UVLO_on
Power On
Detection
PSE identified as type 2 PSE (at)
PSE identified by default as type 1 PSE (af)
PSE Type identification:
Number of Mark Event:
0
1
2
X
Operation Mode:
Figure 9. Hardware Physical Classification Event Sequence
with Mark Events (.at spec)
1st Mark Event    2nd Class Event    2nd Mark Event
nCLASS_AT Indicator
The nCLASS_AT active low open drain output pin can be
used to notify to the microprocessor of the powered device
that the PSE performed a one or two event hardware
classification. If a two event hardware classification has
occured and once the PD application is supplied power by
the NCP1083 DC-DC converter, the nCLASS_AT pin will
be pulled down to ARTN by the internal low voltage NMOS
switch (ARTN is the ground connection of the DC-DC
converter). Otherwise, nCLASS_AT will be disabled and
will be pulled up to VDDL (3.3 V typ) via an internal current
source (20 mA typ) and via the external pull-up resistor.
The following scheme illustrates how the nCLASS_AT
pin may be configured with the processor of the powered
device. An opto-coupler is used to guarantee full isolation
between the Ethernet cable and the application.
Figure 10. Isolated nClass_AT Communication with the Powered Device Application
As soon as the application is powered by the DC-DC
converter and completes initialization, the microprocessor
should check if the NCP1083 detected a two event hardware
classification by reading its digital input (pin IN1 in this
example). If pin IN1 is low, the application knows power is
supplied by a IEEE 802.3at compliant PSE, and can deliver
power up to the level specified by the IEEE 802.3at standard.
Otherwise the application will have to perform a Layer 2
classification with the PSE. There are several scenarios for
which the NCP1083 will not enable its nCLASS_AT pin:
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